Optical wireless communications

ABSTRACT

An optical wireless local area network using line of sight optical links. The base station and terminal stations are provided with optical transceivers which include a transmitter array and detector array. The transmitter array consists of an array of resonant cavity light emitting diodes integrated using flip-chip technology with a CMOS driver circuit. The driver circuit includes constant bias, current peaking and charge extraction. The driver circuitry is compact and can be confined within a region underlying the corresponding light source. The detector array consists of an array of photo diodes, provided with sense circuitry consisting of a pre-amplifier and post-amplifier. The diodes and senses circuitry are also integrated using a flig-chip technique. The light emitter and the detector may include adaptive optical elements to steer and/or focus the light beams.

This application is the U.S. national phase of international applicationPCT/GB01/04628 filed 17 Oct. 2001, which designated the U.S.

The present invention relates to improvements in or relating to opticalwireless communications, particularly to optical wireless links for alocal area network (LAN).

BACKGROUND OF THE INVENTION

The provision of voice data and visual communications to mobile usershas become an important area of research and product development. Thedegree of mobility of users varies widely, from wide area “roaming” atone end of the range, to users within a room requiring a small degree ofmobility but extremely high bandwidth communications at the other end ofthe range. Wireless communication links are essential for providingcommunications with mobile users, and while radio communications areuseful in providing good coverage over large areas, the data transferrates achievable with radio communications are rather limited comparedto the data transfer rates achievable with fixed networks, for instanceusing fibre optics. Thus radio links tend to act as a bottleneck fordata. The advantage of optical links over radio links, namely providingmuch higher bandwidth and thus much higher data transfer rate, iswell-known. Optical local area networks (LANs) have been proposed, andfall into two main types as illustrated in FIGS. 1 and 2 of theaccompanying drawings. Diffuse networks, as illustrated in FIG. 1, use awide angle source 1 and scatter the light from surfaces in the room toprovide an optical “ether” similar to that which would be obtained usinga local-radio transmitter. This produces coverage that is robust toblocking, so that the terminal 3 can receive data despite the directline-of-sight path being blocked by, for instance, a human being 5.However, the multiple paths between the source 1 and receiver at theterminal 3 cause dispersion of the channel, thus limiting its bandwidth.The optical transmitters required are also extremely high power, anddynamic equalisation is required for high bandwidth. Proposed networksusing this approach have provided approximately 10 Mb/s “ethernet” typebandwidth. This low data rate is necessary to avoid the difficultiescaused by multipath dispersion.

An alternative approach, as illustrated in FIG. 2, is to use directline-of-sight paths between a transmitter 7 and terminals 8. These canprovide much higher data rates, but the coverage area provided by asingle channel can be quite small. Therefore providing area coverage andthe ability of users to roam presents difficult problems. There is anadditional difficulty which is that optical channels are subject to eyesafety regulations, and satisfying these regulations is difficult. Theeye safety regulations are particularly strict for near infrared regions(between 700 and 1400 nm), and this means that there are limits on thepower of the sources. Line-of-sight networks also have the problem ofblocking of the channels, by people or objects.

BRIEF SUMMARY OF THE INVENTION

The present invention is concerned with an optical network which usesline-of-sight links, and provides a cellular coverage area. This type ofnetwork is illustrated schematically in FIG. 3 where a base station 10is situated above the coverage area. The base station 10 is providedwith a two-dimensional array of semiconductor light sources 12 whichemit normal to their substrate and illuminate the coverage space with aseries of cells 14. This is achieved by using a lens system 16 to matchsources in the array to a particular angle, to create the desiredcoverage of the space. The use of an array of sources both minimisespower transmitted, as sources not pointing at a detector can be switchedoff, and also each source may transmit different data. Further,detectors not pointing at a source can be turned off. As illustrated inFIG. 3, each terminal within the space has an optical system 16 whichcollects and focuses the light onto a particular detector 18 within adetector array 20. The resulting electrical signal is amplified and adata stream is extracted and supplied to the terminal 8. The use of thearray of detectors allows the angle of arrival of the beam to bedetermined, and hence the direction of the required uplink (from theterminal 8 to the base station) to be determined. The use of the arrayof detectors, rather than a single large detector, advantageouslyreduces the capacitance of each detector, allowing a high bandwidth.Each detector has a narrow field of view, reducing problems with ambientlight, but the use of the array allows a wide overall coverage. AlthoughFIG. 3 illustrates only a transmitter at the base station and detectorat the terminal, in practice each end of the link is a transceiver withan identical transmitter and receiver, to allow bidirectional datatransfer. This system is designed to operate at 980 nm and can providedata rates of 155 Mb/s, but could also operate at any optical wavelengthgiven suitable sources and detectors.

Further details of the light source 12 and detector 18 are illustratedin FIGS. 4 and 5. FIG. 4 illustrates schematically one of the lightsources 12. It comprises an array of surface emitting LEDs or lasers 22which are designed to emit through the substrate of the devices, normalto the substrate. This array is flip-chip bonded to a CMOS siliconintegrated circuit 24. Light from the array is transmitted through alens system 26 which directs individual beams to the correct part of theroom. The assembly includes also a controller in the form of anintegrated circuit 28 and all elements are provided in chip-rackpackaging 27 bonded to a PCB 29. The transmitter optics are shown inFIG. 6 and this consists of two fixed optical elements 30 and 32. Theseare refractive lenses. However, it is also possible to use diffractiveor fresnel optics to obtain the desired coverage pattern. The coveragepattern achieved is illustrated in FIG. 7, which shows a hexagonal arrayof overlapping cells 14.

The receiver is schematically illustrated in FIG. 5 and it consists ofan array of detectors 34, which are photodiodes, which receive theincoming light through the back of the substrate and are flip-chipbonded to an array of sense circuits 36 which convert the signals fromthe detectors into data signals. These are supplied to a controller 38for output to the terminal 8. Light is focused onto the array 34 using alens system 40 placed above the array. The use of an array of detectorsreduces the capacitance of each detector in a similar manner to thereduction of capacitance of the tight sources. Arrays of several hundreddetectors may be needed for systems which offer coverage of over 20sq.m.

The present invention is further concerned with certain components ofthe system. For instance, in one aspect the present invention providesan integrated solid state light emitter comprising a closely integratedand scalable array of solid state light sources with a correspondingarray of drive circuits. Preferably, the emitter comprises a twodimensional unit cell array of solid state light sources formed in anemitter layer and superposed on a corresponding two dimensional unitcell array of respective drive circuits formed in a driver layer, eachdrive circuit producing a shaped drive signal for the correspondinglight source in response to an input logic signal, wherein the surfacearea of each unit cell of the drive circuit array is less than or equalto the surface area of each unit cell of the light source array, wherebyeach drive circuit is confined within a region underlying thecorresponding light source unit cell.

As an alternative, the solid state light sources need not be superposedon the drive circuits. Similarly, the solid state light sources could bearranged other than with respective drive circuits on a 1 to 1 basis.

By confining the area of the drive circuit within the region underlyingthe corresponding light source the light source array is easilyscalable. In other words, the light source array can be made as large asdesired, without particularly increasing the difficulty of fabrication.

A similar approach is used in the detector array. Thus another aspect ofthe invention provides an integrated solid state light detectorcomprising a two dimensional unit cell array of solid state lightdetectors formed in an detector layer and superposed on a correspondingtwo dimensional unit cell array of respective sense circuits formed inan sense circuit layer, each sense circuit for producing a data signalin response to an input light signal to the detector, wherein thesurface area of each unit cell of the sense circuit array is less thanor equal to the surface area of each unit cell of the detector array,whereby each sense circuit is confined within a region underlying thecorresponding detector unit cell.

The key features of a suitable approach to integration are

-   -   (i) That the driver electronics are close to the emitters and        the receiver electronics close to the detectors, in order to        reduce the effects of the interconnection between the        optoelectronic devices and electronics on system performance.

And/or that

-   -   (ii) The integration technology is scalable to large numbers of        separate communications channels.

The invention described here uses a vertical stacking of components toachieve both these aims.

Other approaches might also be used, such as the use of specialisedmaterials processing that allows the emitters and drive circuitry to beintegrated onto a single substrate, and similarly for the receiver.Further it may be possible to integrate detectors, transmitters andelectronics onto a single substrate in this way.

It may also be possible to use a intermediate substrate with emitter anddriver attached separately to the substrate, with this providing theelectrical interconnection between the two components.

Another option is to attach both emitter and detector array to a commonsilicon IC to produce a single component that can both emit and detectfor a higher level of integration.

The light sources in the emitter may be resonant cavity light-emittingdiodes or laser diodes which transmit light at a wavelength of about 900nm or more, more preferably 1400 nm or more. In the detector, theindividual detectors may be photodiodes and the detector may be providedwith optical filter layers for narrowing the bandwidth of lightreceived.

The arrays may be hexagonal close packed arrays and in both the emitterand detector the optoelectronic transducer and its associated electroniccircuitry may be formed in two separate substrates which are thenintegrated together by a flip-chip technique. Preferably the electroniccircuitry is formed in a CMOS circuit.

The drive circuits for the light source's emitter may be adapted toapply a constant bias current, as well as current peaking at the risingedge of the drive signal and charge extraction at the falling edge ofthe drive signal. This achieves a better shape to the response of thelight source. In one embodiment this shaping of the drive signal isachieved using only logic switching circuits to produce edge-triggeredpulses of short width.

The light emitter and/or the detector may include one or more adaptiveoptical elements, such as a spatial light modulator, to steer and/orfocus at the light beam. The element may act as a Fresnel lens and/or ahologram.

In the detectors, the sense circuits may comprise a pre-amplifier and apost-amplifier, with the post-amplifier in one embodiment comprising adifferential amplifier stage followed by a transimpedance amplifier.

These components may be used in an optical wireless local area network(LAN) comprising at least one base station and a plurality of terminalstations. The downlink from base station to terminal may beline-of-sight, whilst if a lower data rate is satisfactory the uplinkfrom terminal station to base station may be an undirected (diffuse)optical link or a radio link.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be further described by way of example, withreference to the accompanying drawings in which:

FIG. 1 illustrates a diffuse optical network;

FIG. 2 illustrates a line-of-sight optical network;

FIG. 3 illustrates a cellular optical network;

FIG. 4 illustrates schematically a transmitter for use in a cellularoptical network;

FIG. 5(a) illustrates schematically a receiver for use in a cellularoptical network;

FIG. 5(b) illustrates schematically a receiver for use in a cellularoptical network;

FIG. 6 illustrates the optical system used in a transmitter;

FIG. 7 illustrates the cellular coverage pattern obtained using thecellular network;

FIG. 8(a) illustrates signals in the driver circuits for the lightsources;

FIG. 8(b) illustrates signals in the driver circuits for the lightsources;

FIG. 8(c) illustrates signals in the driver circuits for the lightsources;

FIG. 8(d) illustrates signals in the driver circuits for the lightsources;

FIG. 8(e) illustrates signals in the driver circuits for the lightsources;

FIG. 8(f) illustrates signals in the driver circuits for the lightsources;

FIG. 9(a) schematically illustrates generation of pulses for currentpeaking and charge extraction in the light source drive circuits;

FIG. 9(b) schematically illustrates generation of pulses for currentpeaking and charge extraction in the light source drive circuits;

FIG. 9(c) schematically illustrates generation of pulses for currentpeaking and charge extraction in the light source drive circuits;

FIG. 10(a) illustrates signals in drive circuits without charge peakingand charge extraction;

FIG. 10(b) illustrates signals in drive circuits without charge peakingand charge extraction;

FIG. 10(c) illustrates signals in drive circuits without charge peakingand charge extraction;

FIG. 11(a) illustrates signals in drive circuits with charge peaking andcharge extraction;

FIG. 11(b) illustrates signals in drive circuits with charge peaking andcharge extraction;

FIG. 11(c) illustrates signals in drive circuits with charge peaking andcharge extraction;

FIG. 12 illustrates the complete driver circuit;

FIG. 13 illustrates the pre-amplifier used in the sense circuit of adetector;

FIG. 14 illustrates the post-amplifier used in the sense circuit of thedetector;

FIG. 15 illustrates the transfer function of the post-amplifier of FIG.14;

FIG. 16(a) illustrates the transient response of the receiver;

FIG. 16(b) illustrates the transient response of the receiver;

FIG. 16(c) illustrates the transient response of the receiver;

FIG. 16(d) illustrates the transient response of the receiver;

FIG. 17(a) illustrates the use of adaptive optical elements to steer andfocus light beams in the optical network;

FIG. 17(b) illustrates the use of adaptive optical elements to steer andfocus light beams in the optical network;

FIG. 17(c) illustrates the use of adaptive optical elements to steer andfocus light beams in the optical network;

FIGS. 18(a) to (c) illustrate different arrangements for local areanetworks;

FIG. 19 illustrates intercommunication between base stations in a localarea network;

FIGS. 20 and 21 illustrate the power coupled to the detector when usingadaptive optical elements;

FIG. 22 illustrates a light source array;

FIG. 23 illustrates a detector array;

FIG. 24 illustrates a nomograph;

FIG. 25 illustrates diagrammatically an alternative receiverarrangement; and

FIG. 26 illustrates diagrammatically a further alternative receiverarrangement.

DETAILED DESCRIPTION OF THE DRAWINGS

As indicated above, the light source in the system consists of an arrayof light emitters, in this embodiment resonant cavity light emittingdiodes. The diodes are driven by respective driver circuits implementedas current sources. Thus the driver circuit converts a digital voltageinput signal into a train of current pulses. In order to improve theoptical rise time and fall time of the LED, the drivers provide a smallbias current I_(B) to the LED at all operational times. This keeps thespace-charge capacitance charged, avoiding a delay in carrier injectionand a consequent delay in light output. To further improve the rise timeand fall time, peaking current is injected in the form of a currentspike I_(P) into the diode terminal at the start of each low to hightransition in the data signal. This is followed by a controlled decay tothe steady high level of the data signal. Fall-time at the end of theinput signal can be reduced by injecting a reverse current I_(R) intothe diode at the beginning of each high to low transition. This is knownas charge extraction. FIG. 8 illustrates the input data signal at FIG.8(a) (which is 5V peak-to-peak and has 0.1 ns rise and fall time), theconstant bias current I_(B) in FIG. 8(b) and the basic drive signal(without current peaking or charge extraction) at FIG. 8(c). FIGS. 8(d)and (e) illustrate the current peaking and charge extraction currentsrespectively, and FIG. 8(f) indicates the actual drive signal formed bycombining I_(B), I_(M), I_(P) and I_(R). The result of using the drivesignal I_(LED) is that the output of the LED more accurately reflectsthe shape of the input data signal.

In order that large arrays of light sources can be constructed it isadvantageous if the drive circuitry for each light source is of similaror smaller surface area than the light source itself. This means that anintegrated component can then be produced in which the drive circuitryfor each light source underlies the corresponding light source. Thearray is then scalable, i.e. it can be made as large as desired withoutfabrication problems caused by the drive circuit for one light sourceextending under another light source.

One embodiment of drive circuitry achieving this will be described withreference to FIGS. 9 to 12. In this embodiment the current peaking andcharge extraction pulses are formed as edge-triggered pulses of a shortwidth. This has the advantage that no external components, such ascapacitors or resistors are required, meaning that the driver circuitcan be fabricated with all components on an integrated circuit. FIG. 9illustrates schematically the generation of the short pulses. The inputdata signal is applied to a string of inverters and a two input logicgate as illustrated in FIG. 9(a) The inverters effectively delay thedata pulse by a short interval. The type of the logic gate thendetermines whether the output pulse signal is triggered on the risingedge or the falling edge of the data signal. From FIG. 9(b) it can beseen that a NAND logic gate produces a negative pulse on the rising edgeof the signal. This pulse can be used for current peaking. A NOR logicgate generates a short positive pulse on each falling edge of the datasignal, which can be used to form the charge extraction pulse. The widthof the pulses is determined by the gate delay introduced by the inverterstring. With appropriately designed inverters, the length of the delayintroduced may be controlled externally.

FIG. 12 illustrates the full driver circuit. The input and output pinsare listed and described in Table 1 below.

Pin name Signal type Function V_(IN) Logic Data signal V_(MOD) LinearLED modulation current adjust V_(BIAS) Linear LED quiescent currentadjust V_(EXT) Linear Charge extraction adjust V_(INJ) Linear Currentpeaking adjust

In FIG. 12, transistor pairs M7-M8, M9-M10 and M11-M12 form a chain ofinvertors for the NAND-gate pulse generator 50. Transistors M13, M14,M15 and M16 form a NAND gate 51. The output pulse from this generatordrives the gate of pass transistor M17. This pass transistor conductsthe drain current from M18 (determined by V_(INJ)) for a very shortduration. This injection current is applied to the LED represented byequivalent circuit 48.

Transistor pairs M19-M20, M21-M22 and M23-M24 form the invertor stringfor the NOR-gate generator 52. The NOR-gate is made of four transistorsM25, M26, M27 and M28. This pulse generator drives pass transistor M30and the reverse current produced is determined by the amount of currentthat M29 conducts, which, in turn, is determined by the magnitude ofV_(EXT). Transistors M31-M38 are invertor buffers which enable the datasignals to drive subsequent loads.

The bias current I_(B) is provided by transistor M6. The input datasignal drives a CMOS switch (comprising transistors M2 and M3) whichconduct the current from transistor M1 to the input of the currentmirror formed by transistors M4 and M5. This current is then amplifiedto provide the modulation current I_(M) which is the basic drive signalfor the diode.

FIGS. 10 and 11 illustrate the signals in the driver circuit. FIG. 10illustrates the effect of driving the LED 48 without any current peakingor charge extraction. Thus the input is shown at FIG. 10(a), FIG. 10(b)illustrating the total diode current (ie. the total current intoequivalent circuit 48) with FIG. 10C illustrating the resistive diodecurrent (ie. the current down the resistive branch of the equivalentcircuit 48). The resistive current corresponds to the light output. Itcan be seen that the waveform has long rise and fall times, and is notshaped like the data signal.

FIG. 11 shows the effect of driving the LED using the shaped drivesignal, which includes current peaking and charge extraction. Again FIG.11(a) shows the data signal, FIG. 11(b) shows the total LED current withcurrent peak P, steady drive signal Q, and charge extraction S. FIG. 11Cillustrates the resistive diode current, corresponding to theillumination. It can be seen that the rise time and fall time have beensignificantly reduced, the waveform corresponding much more closely tothe input data signal.

The light sources are 980 nm bottom emitting Resonant Cavity LEDs, grownon double polished n+ GaAs substrates. The emission wavelength andemission angular beam profile are set by the emission wavelength of theactive region (quantum wells) and the resonance wavelength of thecavity. The difference between the two wavelengths is known as detuning,and this is optimised to maximise the power received at thephotodetector for the particular optical system used. The particularwavelength within this rage (980-1000 nm) is chosen to be (ideally)within an optically quiet region of the ambient light optical spectrum.

The plan view of the light source array is shown in FIG. 22. The sources22 are on a hexagonal pitch of 300-500 μm or so. The hatched contacts220 are the p contacts, on the rear of the device, and the solidcontacts 222 are the n contacts.

The light source array is flip-chip bonded to the CMOS driver circuitsformed on a separate substrate to produce an integrated light emitter.

The receiver uses an array of photo diodes (34) each supplying itssignal to a respective sense circuit consisting of a pre-amplifierfollowed by a post-amplifier. The pre-amplifier is a three stagetransimpedance amplifier with an NMOS load at the output of each stageto control gain and stability. This is shown schematically in FIG. 13.Each stage consists of a CMOS inverting amplifier with a diode-connectedNMOS load. The amplifier is designed to have a −3 dB bandwidth of 217MHz. The bandwidth of each stage is set as 939.93 MHz. This correspondsto a phase shift of 13° per stage at the gain-bandwidth. The completeamplifier also includes a feedback resistor 57. The width and length ofthe transistors are defined by a special algorithm based on the use of aprecomputed nomograph shown in FIG. 24.

The nomograph is computed from known parametric data corresponding tothe CMOS process to be used. It relates DC bias conditions, bandwidth,stability and gain with transistor dimensions W1, W2 and W3 in a mannernot practicable using traditional design methods. This approach allowsoptimised values to be chosen for the transistor dimensions.

The post-amplifier is schematically illustrated in FIG. 14. It is athree stage amplifier. The first stage is a DC-coupled invertingamplifier 58 with DC stabilisation to maintain correct operatingconditions. The stabilisation circuit also serves to curtail the lowfrequency response to reduce the effect of unwanted low frequency noise.The second stage is a differential amplifier 59 which produces an outputcurrent that is amplified by the third stage of amplification 60, atransimpedance amplifier. A final stage of amplification consists of aninvertor and a diode-coupled NMOS transistor 61. The use of adifferential amplifier allows, where desired and with the addition ofthe necessary extra circuit elements, signals from different detectorsto be combined together. This allows a plurality of signals of differentstrengths to be combined together in different proportions depending ontheir strengths.

The detectors are substrate illuminated InGaAsP PIN diodes grown on InPsubstrates. These will operate at both 980 and 1500 nm. The I-region isrelatively thick for these types of device, in order to minimise thecapacitance. The bandwidth of the circuit is limited by the capacitanceand the transit time for carriers to pass across the detector junction.These two are competing and preferably the detectors work at an optimumpoint between these effects. The thickness of the detector and the DCbias voltage of the detector are optimised to achieve this.

The plan view of the detector array is shown in FIG. 23. The detectors230 are close packed on a hexagonal pitch of 300-500 μm or so, with onecontact 231 per device, and ground contacts 232 around the periphery.

The detector picks up the desired power (at a specified wavelength) andoptical noise over a range of wavelengths. Narrowing the opticalbandwidth by integrating optical filters with the detectors can beachieved using the structure shown in FIG. 5B in which filtering isprovided by the layer (a) consisting of InGaAsP of an appropriatecomposition.

The optical receiver is fabricated using CMOS process technology. Thepreamplifier and post-amplifier are both formed in the same substrate,both fitting within the surface area of the photo diode supplying them.In fact, of course, an array of amplifiers is formed, corresponding tothe array of photo detectors. The sense circuitry and detector array areflip-chip bonded together to form an integrated device. Except for thephoto diode detector and decoupling capacitors, the receiver chiprequires no external circuit components. In this implementation threesets of power/ground supplies are used for the analog circuitry andsubstrate. This prevents noise coupling from switching (digital)circuitry onto sensitive (analog) circuitry through the low resistivepaths to the power supply. Externally the analog and substratepower/ground supplies are connected in order to suppress thesource-to-bulk noise voltage effect that can corrupt the transistordrain current.

The transfer function from the post-amplifier voltage input to finaloutput is illustrated in FIG. 15.

FIG. 16 illustrates a simulation of the transient response of thereceiver circuit under typical conditions. FIG. 16(a) illustrates theinput current signal, FIG. 16(b) the pre-amplifier output voltage, FIG.16(c) the post-amplifier output voltage and FIG. 16(d) the final bufferoutput voltage.

One of the chief difficulties in a fixed optical wireless design is thepower budget. Even with fixed optics, only a small fraction of theavailable power within a cell is received at the photo diode. Thisproblem is compounded by the large fall off in optical power densitytowards the edge of the cell. In order to optimise the power budget ofthe optical link, it is possible to focus the light from the transmitteronto the detector, or to steer the light beam onto detectors at thereceiver. This is achieved by using an adaptive optical element whichcan take the form of a Fresnel lens or a computer generated hologram.These can be achieved using a spatial light modulator which is anelectronically addressed, pixelated device capable of binary phasemodulation. For instance, devices which use nematic liquid crystals andhaving a pixel pitch of 42 micrometers with 640 by 480 pixel resolutionare available. Patterns can be programmed into the device (to define thestate of each pixel) such that the device acts as a desired opticalelement.

FIG. 17(a) illustrates the use of an adaptive optical steerer 70 infront of the fixed optical element 26 and source array 22. The adaptiveoptical steerer 70 is effective to move the emitted beams within theircells.

FIG. 17(b) illustrates the use of the adaptive optical elements 72 tofocus and steer the beams from the source array 22. The central beam 72illustrate the output with the adaptive optics inactive, whereas beam 74illustrates the effect of focussing and steering the beam using theadaptive optical element.

FIG. 17(c) illustrates the use of an adaptive optical element 76 in thereceiver. The element is programmed to steer and focus the beam throughthe fixed optical element 40 on to the detector array 34. The adaptiveoptical element can be programmed to steer the beam to a particulardetector in the array and this configuration allows light from multipletransmitters to be focussed on to the same detector, for instance toallow “handover” between base stations. FIG. 17(d) illustrates acomparative example which lacks the adaptive optical element. It may bepossible to reduce the number of elements in the array to a singledetector with the use of adaptive optics.

Rather than using a spatial light modulator, deformable mirrors or otheradaptive optical elements may be used.

FIG. 20 illustrates how the power coupled to the receiver varies as itis displaced from its central position when the adaptive element isdesigned to focus to a 1×1 target area. In FIG. 21, a larger (3×3)target area is used creating a larger “spot” of light so the receiver isless sensitive to displacement from its desired position.

FIG. 25 illustrates an alternative receiver which uses a single detector250 rather than a detector array. In this embodiment the detector 250 isa photomultiplier, preferably a solid-state photomultiplier such as aPhotek PMT 110 or the like. Photomultipliers have a low capacitance, andthus the use of a photomultiplier also has the advantage of allowing thedetector to have a large area and a high bandwidth and they are muchmore sensitive than photodiodes. The use of a single detector ratherthan an array removes the need for processing circuitry to combine thesignals from several detectors.

In order that the receiver can track the light source and can rejectnoise (i.e. extraneous light from other angles), an optical shutter 252is positioned over the single detector so that different areas of thedetector can be selectively exposed as at 252 a or shut-off as at 252 b.A spatial light modulator (SLM) may be used for this such as CRL 128×1282D SLM. The optical shutter 252 may have an essentially binarycharacteristic, such that its areas 252 a, b etc are “on” or “off”.Alternatively an analogue (variable transmittivity) may be used to allowdifferent proportions of the input signal from different directions tobe incident upon the detector, and thus to combine in different weights(according to the transmittivity of the optical shutter areas). This canimprove noise rejection by allowing combination of signals in proportionto their signal-to-noise ratios.

As with the previous receiver embodiment a lens system 254 collects theincoming light and in combination with the optical shutter 252 gives theangular sensitivity to the receiver.

Rather than using a single detector and optical shutter, the opticalshutter may be combined with an array of small area detectors 260 asshown in FIG. 26. The signals from the individual detectors 260 may becombined through a simple summing circuit 262. Thus the angularselectivity is provided optically by lens system 264 and optical shutter262. This allows simplification of the signal processing electronics.

The use of the optical shutter 252, 262 allows the overall shape of thedetector area to be varied as desired which can allow compensation foralterations and imperfections in the optical system.

The receiver may be used as a “hub” in an optical LAN allowing thereception of time-multiplexed signals from different light sources.

In the system described above, the data links are symmetrical in thateach end of the link contains an identical transmitter and receiver.However, there are circumstances where a high bandwidth is only requiredin one direction, such as for web browsing. In this case, other modes ofoperation are possible. FIG. 18 illustrates various configurations. FIG.18(a) shows the bidirectional system. In FIG. 18(b) only the down linkis a direct line of sight optical link, with the up link being via radio(and thus of lower bandwidth). In FIG. 18(c) the up link is a diffuseoptical link (again of lower bandwidth). The system may also includemultiple base stations as illustrated in FIG. 19, each interconnectedwith optical links. A transceiver 18 is also provided for an externalwireless link which can be optical or radio. For clarity, the basestations are not shown in FIG. 19.

Of course it is possible for the transceivers at the base station andreceiver to be provided with both optical and radio or optical line ofsight and optical diffuse transceivers. These transceivers could be usedselectively according to bandwidth, cost or any other criteria. It ispossible for the radio link to be used for data requests, and theoptical link to be used for transfer of data when the user is within theoptical coverage area.

1. An integrated solid state light emitter comprising a two dimensional unit cell array of solid state light sources formed in an emitter layer and superposed on a corresponding two dimensional unit cell array of respective drive circuits formed in a driver layer, each drive circuit for producing a shaped drive signal for the corresponding light source in response to an input logic signal, wherein the surface area of each unit cell of the drive circuit array is less than or equal to the surface area of each unit cell of the light source array, whereby each drive circuit is confined within a region underlying the corresponding light source unit cell.
 2. An integrated solid state light emitter according to claim 1, wherein the emitter layer is formed in a light source substrate through which the light sources emit light in a direction substantially normal to the substrate.
 3. An integrated solid state light emitter according to claim 1 wherein the light sources are resonant cavity light emitting diodes.
 4. An integrated solid state light emitter according to claim 1 wherein the light sources are laser diodes.
 5. An integrated solid state light emitter according to claim 1 wherein the light sources emit light at a wavelength of 900 nm or more.
 6. An integrated solid state light emitter according to claim 1 wherein the light sources emit light at a wavelength of 1400 nm or more.
 7. An integrated solid state light emitter according to claim 1, wherein at least one of the light source array and drive circuit array is a hexagonal close packed array.
 8. An integrated solid state light emitter according to claim 1, wherein the light source array and the drive circuit array are formed separately in respective substrates which are integrated together.
 9. An integrated solid state light emitter according to claim 8, wherein the two substrates are integrated together by a flip-chip technique.
 10. An integrated solid state light emitter according to claim 1, wherein the drive circuit array is formed by a CMOS circuit.
 11. An integrated solid state light emitter according to claim 1, wherein each drive circuit comprises a bias current source for supplying a constant bias current to the corresponding light source.
 12. An integrated solid state light emitter according to claim 1, wherein each drive circuit comprises a current peaking source for supplying a current pulse to the corresponding light source in time with the rising edge of a square drive signal.
 13. An integrated solid state light emitter according to claim 1, wherein each drive circuit comprises a charge extraction circuit for supplying a charge extraction signal to the corresponding light source in time with the falling edge of a square drive signal.
 14. An integrated solid state light emitter according to claim 1, wherein each drive circuit incorporates a delay circuit formed completely as an integrated circuit.
 15. An integrated solid state light emitter according to claim 14 wherein said delay circuit is constituted by logic gates.
 16. An optical transceiver comprising an integrated solid state light emitter comprising a two dimensional unit cell array of solid state light sources formed in an emitter layer and superposed on a corresponding two dimensional unit cell array of respective drive circuits formed in a driver layer, each drive circuit for producing a shaped drive signal for the corresponding light source in response to an input logic signal, wherein the surface area of each unit cell of the drive circuit array is less than or equal to the surface area of each unit cell of the light source array, whereby each drive circuit is confined within a region underlying the corresponding light source unit cell, and an integrated solid state light detector comprising a two dimensional unit cell array of solid state light detectors formed in an detector layer and superposed on a corresponding two dimensional unit cell array of respective sense circuits formed in an sense circuit layer, each sense circuit for producing a data signal in response to an input light signal to the detector, wherein the surface area of each unit cell of the sense circuit array is less than or equal to the surface area of each unit cell of the detector array, whereby each sense circuit is confined within a region underlying the corresponding detector unit cell. 